Mobiveil, Inc., a fast-growing supplier of silicon intellectual property (SIP), platforms, and IP-enabled design services, today announced its Compute Express Link (CXL) 2.0 Design IP and successful completion of CXL 1.1 validation with Intel’s CXL host platform.
Mobiveil’s CXL controller IP (COMPEX) is a highly configurable, low-latency CXL controller that supports host and device modes for several high-performance applications, such as data center accelerators, memory expanders, artificial intelligence/machine learning, and special applications.
The COMPEX controller IP is designed for CXL 2.0 specification and supports host and Type 1, Type 2, and Type 3 devices. COMPEX also supports dual mode, in which it can be configured to operate either as a host or any of the device types.
COMPEX supports up to 16 lanes on a flex bus interface and is compliant with the PIPE 5.2 specification. It provides a simple packet-based interface-to-user logic that supports 128-bit, 256-bit, and 512-bit data path widths and provides a low-latency path for easy integration into a customer ASIC. An implementation can choose one of the data path widths based on the number of lanes and target technology to get low-latency and optimized power consumption from COMPEX controller.
For CXL.io, COMPEX uses Mobiveil’s PCI-SIG–compliant GPEX controller and adds highly efficient and configurable CXL.mem and CXL.cache layers for a low-latency coherent path. The COMPEX controller IP version 1.1 recently completed system-level validation using future Intel Xeon Scalable processors codenamed Sapphire Rapids.
“From the moment we kicked off the CXL IP development, our IP engineering as well as our system engineering teams focused on delivering high-performance, high-quality IP validated in a system-level environment,” said Gopa Periyadan, Mobiveil’s COO. “We worked closely with the Intel CXL validation team to make sure these goals were met. Before porting the COMPEX controller to Mobiveil’s FPGA platform, it was fully verified for functionality and compliance using Avery Design Systems’ CXL Verification IP. This newly validated IP will help our customers accelerate high-performance applications.”
“We are pleased to see CXL 1.1 Type 2 Device IP seamlessly interface with our Sapphire Rapids CPU using the CXL protocol and successfully execute data transfers on CXL.mem and CXL.cache paths,” said Mahesh Wagh, senior principal engineer in Intel’s I/O Technology and Standards Group. “The availability of Mobiveil’s CXL IP will help accelerate the adoption of the CXL standard and the proliferation of CXL devices in the market.”
Mobiveil’s controller has a simple, configurable, and layered architecture independent of application logic, PHYs, implementation tools, and, most important, the target technology itself. It allows the user to migrate between standard cell technologies and FPGAs. The controller’s flexible backend interface can be integrated into a wide range of applications.
The CXL controller architecture optimizes link utilization, latency, reliability, power consumption, and silicon footprint. It handles PCI Express ordering rules and implements multiple virtual circuits (VCs) and associated flow control logic in both directions. The packet-oriented user logic interface also supports PIPE 5-compliant PHYs and flexible lane ordering and support for lane reversal.
Mobiveil’s IP team has more than 15 years of experience developing IP blocks for several high-speed serial interconnect solutions. The interface IP designed by Mobiveil is integrated in hundreds of system-on-chip designs and shipped in millions of devices.
Mobiveil’s CXL 1.1-based COMPEX Controller IP is available for licensing now. It can be targeted to FPGA, eASIC and Structured ASIC technologies. The CXL 2.0-based COMPEX controller will be available in Q1 2021. Pricing is available on request. More information on Mobiveil’s COMPEX IP is found at the Mobiveil website, or email email@example.com.